EECS Colloquium

                                                                                      Host: Sung-Min Hong / Language: English

Thursday, September. 25, 2025, 16:00~

ZOOM

Flip FET(FFET) as the Next Generation Stacked Transistor Technology: From Processes to Devices and to Chips

Prof. Heng Wu

Department of Integrated Circuits, Peking University

[Abstract]                                                                                                                                                                                                                                                                                                                                                                                                                     

 In this talk,  we will reviewed the Flip FET (FFET), a newly proposed 3D stacked transistor architecture, in the aspects of process development, design enablement and block-level benchmarks. Two layers of transistors and

interconnects are formed on each side of wafer and back-to-back stacked, featuring a much more manufacturing-friendly process flow with low aspect ratio (AR). Standard cell (STC) libraries with minimum 2.5 track height (2.5T) 

design are established, proving further scaling possibility and better intra-cell routability over CFET thanks to dual-side signal tracks. New concepts of dual-side global interconnects are introduced and the P&R result of a RISCV32I

core further validates the superiority of FFET. In the end, the FFET's extension of F3D integration will be discussed. It has great flexibility to do dual-sided integration of complex circuits, such as memory stacking, memory to logic

stacking, delivering great flexibility and extendibility for future’s electronic applications.

For the slides, I am still polishing it.

[Short Biography]

Heng Wu is an Associate Professor in the School of Integrated Circuits at Peking University. He received the Ph.D. degree in Electrical and Computer Engineering from Purdue University in early 2016. After graduation,

he joined IBM T. J. Watson Research Center in Albany N.Y. USA as a research staff member. He joined Peking University in early 2023. 
His research focuses mainly on high speed and low power CMOS devices and circuits, transistors architecture and design technology co-optimization(DTCO). Prof. Wu has published more than 80 papers and received

4 best paper awards (including VLSI Symposium). He has filed more than 500 patents. He was an IBM Master Inventor and recipient of IEEE Paul Rappaport Award.